EPFL is responsible for developing LNAs based on parametric amplification techniques in (Bi)CMOS technologies, needed to demonstrate qubit readout at sub-10mW power consumption for operation at 4K and below. EPFL will also develop digital integrated circuits for cryogenic interface to SNSPDs and extensively test active components in SiGe transistor farms and create compact EKV models.

EPFL will take care of  extensively test active components in SiGe transistor farms and create compact EKV models for NMOS and PMOS transistors compatible with DC and RF operation. EPFL will also characterize passive components, such as capacitances and resistances from 4 K to RT using simplified passive circuits. Selected inductors and transformers will also be modelled at 4 K for use in circuits and systems.

EPFL will design a parametric amplifier compatible with 22nm and 28nm FDSOI technology to operate at sub-4K temperatures. The amplifier will feature a gain of 10dB and a NET below 4 K, while achieving a power dissipation lower than 1mW. It is intended for scalable interfaces with qubit, eventually enabling multiple low-noise readout channels.

EPFL will design and test optical receivers operating at sub-4K temperatures. The receiver, based on single-photon avalanche diodes (SPADs) will be cryo-CMOS compatible and will enable optical links as well as optical sensors for non-invasive temperature detection and monitoring.

More information on https://www.epfl.ch/labs/aqua/