Deliverables

WP1: Materials

D1.1: Silicon and III-V substrates evaluation for cryogenic microsystems (due January ’27)
D1.2: Line resistance & TCR values of actual interconnects (due July ’26)
D1.3: Report on midlow opacity contacts (due September ’25)
D1.4: TWPA amplifiers evaluation (due June ’26)
D1.5: ALD dielectrics and metal nitrides for cryogenic temperatures (due January ’27)
D1.6: Engineering of defects, workfunction metals and dipoles for cryo gate stack (due September ’26)
D1.7: Cryomaterials roadmap (due June ’26)

WP2: Multi-scale Physics and Data-driven Modelling

D2.1: Workflow and Library of Disordered Structures (due September ’25)
D2.2: Parameter library of defect properties (due September ’26)
D2.3: Initial version of TCAD simulation deck for 28 nm FDSOI
D2.4: Final version of TCAD simulation deck for 28 nm FDSOI (due March ’27)
D2.5: Multiqubit modelling software tool coupled with computer-aided design capabilities (due September ’25)
D2.6: Technological defect sensor design and simulations (due September ’26)
D2.7: Tentative qubit compact model (due March ’26)
D2.8: Final qubit compact model (due March ’27)
D2.9: Transistor characterization and parameter extraction
D2.10: FDSOI linear and non-linear substrate modelling (due September ’25)
D2.11: Models for cryogenic HBT and MOS devices are fully developed (due September ’26)
D2.12: Initial CMOS quantum dot device characterization and control algorithms
D2.13: Final CMOS quantum dot device characterization and control algorithms (due September ’27)

WP3: Classical Devices and Circuits

D3.1: Low-noise silicon quantum dots at temperatures above 1K
D3.2: Flicker noise for MOSFET and polyresistors down to cryo temperatures (due March ’26)
D3.3: Low frequency noise benchmark of FDSOI and bulk-Si MOSFETs (due February ’27)
D3.4: Reliability and variability of FDSOI devices (due March ’27)
D3.5: Thermalization of FDSOI devices at mK temperatures (due March ’26)
D3.6: Self-heating and noise characterization in nMOS devices (due March ’26)
D3.7: Noise control by in-situ heating (due March ’27)
D3.8: Design, fabrication and characterisation of ultra-low dissipation cryogenic FDSOI electronics (due September ’26)
D3.9: Ultra-low power FDSOI multiplexer design (due March ’27)
D3.10: Transceiver specifications and feasibility study
D3.11: Design and measurement results of transmitter (due March ’27)
D3.12: Design and measurement results of receiver (due March ’27)
D3.13: Design and fabrication of LNAs (due June ’26)
D3.14: Temperature controller design and fabrication (due January ’27)

WP4: Emerging Devices and Components for Cryo-
Systems

D4.1: SNSPD array (due September ’26)
D4.2: SNSPD readout (due September ’26)
D4.3: Cryo-SPAD design and fabrication (due March ’27)
D4.4: Interim spin qubit fabrication and characterization report
D4.5: Final spin qubit fabrication and characterization report (due September ’26)
D4.6: Cryogenic memory Device performance (due March ’26)
D4.7: Cryogenic memory model parameters and benchmark (due November ’26)
D4.8: Nanowire switch design and prestudy and system ADC/DAC specification
D4.9: Nanowire switch fabrication (due March ’26)
D4.10: Nanowire switch performance (due March ’27)
D4.11: First stage of design, technology and testing procedures of low phase noise microwave sources (due September ’25)
D4.12: Fully manufactured low phase noise microwave sources (due December ’26)

WP5: 3D Integration and Packaging

D5.1: New bonding equipment hardware and process capabilities (due March ’26)
D5.2: Qubit bonding processes on silicon and substrate (due January ’27)
D5.3: Cooler integration process (due September ’26)
D5.4: Single-photon detector packaging and functional demonstrator (due January ’27)
D5.5: Cryo-CMOS packaging (due December ’26)

WP6: High-throughput Cryogenic Test and Measurement

D6.1: Cryogenic 1-2K test systems (due September ’25)
D6.2: Optimized cryogenic 1-2K test systems (due September ’26)
D6.3: Cryogenic 20 mK device test system (due September ’25)
D6.4: Preliminary device and wafer measurements and correlation analysis (due December ’25)
D6.5: Device and wafer measurements and correlation analysis (due January ’27)
D6.6: First LNA characterization datasheets from 77K down to 1K (due December ’25)
D6.7: Final characterization datasheets of all available LNAs (due December ’26)

WP7: Demonstrators

WP8: Dissemination and exploitation

WP9: Project Management

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