The requirements on material and substrate properties at cryogenic temperatures can be quite different from those in traditional CMOS fabrication processes. Some examples of these are: 1) highly resistive, low-loss silicon substrates to minimize RF losses and thermal coupling between devices or 2) super thermalization substrates to ensure a good thermalization of classical cryo-CMOS circuits and qubits to the base temperature of the fridge.

After the substrate, the next most critical component for successful device operation is the presence of a high-quality gate oxide. Since cryogenic operation of devices provides much lower thermal energies, the well-understood defect models of normal CMOS devices are no longer valid. Not only do devices fabricated using conventional materials require more rigorous testing at cryogenic temperatures to understand the behaviour of defects and how they affect cryogenic device performance, but the non-standard ALD-based materials (e.g., gate oxides, work-function shifting layers, and ferroelectric materials) frequently used in state-of-the-art quantum and other beyond-CMOS devices also need proper characterization under relevant conditions.

Another important field of innovations is the development of scaled metal interconnects for the back-end of line since a large part of cryo-CMOS performance benefits are owed to the improvement of gate RC delay due to reduced metal resistances and one of the major challenges of densely scaled spin qubits is still the fan-out from the numerous qubit gates to the upper metal layers.

Finally, thin film development for low-temperature, high-quality dielectrics as well as titanium-nitride (TiN) and niobium-titanium-nitride (NbTiN) based superconducting thin films will help to show the feasibility of optimizing the gate-stack of CMOS devices for cryogenic temperatures and allow the fabrication of scalable single-photon detectors.