Many quantum computers use cryogenic pre-amplifiers for readout, but major parts of the classical control and electronics like signal processing, memory, or the digital qubit interface are still located at room temperature. As the number of qubits keeps scaling up, providing these signals from classical circuits at room temperature to the qubits will become an increasingly difficult problem not only in terms of the number of wires to be brought to the mK stage, but also in terms of latency times and signal integrity.

Cryogenic CMOS Devices:

For advancing cryogenic CMOS solutions for quantum computing, cryogenic sensing and space applications, it is of utter importance to understand the noise performance as well as their origins under cryogenic conditions. By combining the expertise of the different partners, noise effects and its origins are investigated in depth to enable well-directed process optimization of MOS gate stacks and CMOS devices for cryo-CMOS applications. ARCTIC will explore the differences and complementarities of different SH extraction techniques and propose possible optimization routes such as the minimization as well as the fair modelling of SH at cryogenic temperatures.  Moreover, we will study the effects of thermal cross-coupling between adjacent devices to understand the proximity effects in heterogenous integration schemes or adjacent devices.

Cryogenic CMOS circuits:

In terms of circuit design, we will demonstrate a scalable RF multiplexer with at least SP8T configuration and record low static power consumption (< 0.1 uW) and carrier temperature (< 100 mK), targeting scalable low frequency characterization of superconducting and other qubit technologies.

We will develop the first-ever cryogenic high-speed (> 10Gbit/sec) transceiver and demonstrate a bidirectional medium-range communication between two developed transceivers, one located at the 4 K and the other placed at room temperature. To improve the transceiver energy efficiency in Joule/bit, we will introduce a new family of flip-flops, phase interpolators, and phase detectors based on the charge-steering principles. To maximize the transceiver bit rate, high-order pulse-amplitude modulation schemes will be adapted, enabled by the lower thermal noise at cryogenic temperatures.

The fabrication of LNAs in three different technologies is included to benchmark the benefits and drawbacks of each of them. More precisely, we will combine the benefits of low-noise InP and low-power SiGe technologies and develop hybrid InP/SiGe LNAs for ultra-low noise and reasonable power consumption. We will develop SiGe LNAs for state-of-the-art noise performance and push CMOS LNA noise below 8K. Furthermore, SiGe LNAs for 12 to 30 GHz operation will be developed.

On top of that, high-speed analog to digital converters with ultra-low power consumption will be developed in order to be compliant with massive qubit readout. In particular, we will take advantage of the back gate control of the MOS transistors of FDSOI technologies to reduce dramatically the power consumption of the ADC comparator.