Cryogenic Integrated Photonics and Microwave Systems:

We will demonstrate a large, scalable Superconducting Nanowires Single Photon Detector (SNSPD) imaging system consisting of an array of detectors integrated with cryogenic readout electronics. We will design a scalable semiconductor integrated readout design operating at 4K near the detectors, optimized for minimum power dissipation for a given application jitter requirements and not requiring any 50Ω matching. We will design and fabricate the compact and scalable cryo-CMOS readout electronics, including a low-noise amplifying stage with active quenching and latching detection and a cascaded time-to-digital converter (TDC) for time stamping, resulting in detection performance being only limited by the SNSPD jitter.

A photonics-based approach will be used to generate ultra-low phase noise microwave in C and X-bands. In this approach, the photonic oscillator, a mode-locked femtosecond laser, is located outside the cryostat and an optical fibre brings the ultralow jitter optical pulse train into the cryostat which illuminates a high-power fast photodiode operated at low temperatures and close to the electronic circuitry. Due to an innovative system engineering and modular building blocks (mode-locked laser and cryocooled photodiode), a phase noise floor of –180 dBc/Hz at C or X-band carrier frequency shall be reached.

Another solution for generating quantum-based microwave signals of extremely high quality is the combination of BiCMOS chips and a Josephson arbitrary waveform synthesizer (JAWS) at cryogenic temperatures. Therefore, we will demonstrate a fully cryogenic integration to drive scalable JAWS chips to generate quantum-based microwave signals of extremely high quality. Typically, state-of-the-art high-end microwave synthesizers has harmonic disturbances and are spurious in the range of -30 dBc. The JAWS based microwave generators developed by ARCTIC are expected to be at least 10 times better.

Silicon based spin qubits:

In ARCTIC, we will demonstrate fabrication and testing of FDSOI-based spin qubit devices. We will leverage the back gate to pull the qubit away from the interfaces and thus shield it from charge disorder. The technology will be further improved by large scale electrical measurements and fast process development cycles as well as development of long 1D and quasi-2D spin qubit arrays. Finally, we will demonstrate the feasibility of monolithic integration of cryo-CMOS devices with the qubits on the same wafer.

Novel cryogenic memory concepts:

The ARCTIC partners will improve the energy efficiency and latency of cryogenic memory components by the development of non-volatile memory with non-destructive readout for refresh-free operation. This will be achieved with the design and fabrication of ferroelectric field-effect transistors (FeFETs) and ferroelectric tunnel junctions (FTJs) with low off current and standby power, and by designing in-memory computing (IMC) architectures. Integration density will be improved by novel design concepts for higher on-current density in scaled FTJs or the use of atomically thin 2D semiconductors and vertical nanowire transistor structures for improved scalability.

Finally, the understanding of device physics – especially charge-trapping and trap assisted tunnelling mechanisms and noise – as well as thorough material and interface structural characterization will help to improve cryogenic performance reliability, yield and endurance.

Nanowire transistor electronics:

The partners will develop a set of cryogenic III-V nanowire circuits to be used for signal in- and output from quantum devices. The circuits will consist of switches including new topologies involving bootstrapping techniques to be used for a direct sampling concept based on a time interleaved ADC. The effort will include material development with extending patterning and nanowire growth up to 4” wafers as well as detailed studies of gate-stack properties at cryogenic  temperatures, relating the III-V stacks to other related material systems. The transistors will be optimized for reduced parasitics, fabricated and then also characterized at cryogenic conditions.