Many cryostats are either designed for manual measurements or come with highly customized, static sample holders and signal lines, which prohibits multiplexed or wafer-level measurements on such systems. However, especially for temperatures ranging from 1K to 4K, cryogenic multiplexing solutions and wafer-level probe stations are feasible and enable a significantly higher throughput, meaningful statistics, and faster learning cycles.

Cryogenic measurement test systems:

We will develop a variety of test setups for high throughput testing along the whole testing chain, for both silicon quantum devices, SNSPDs & NIS junctions and LNAs. We will develop a testing system at 1 K composed of cryostat, control hardware and software and tightly integrate these components to provide maximum testing speed. We will also use our partners’ cryoprobers with operating temperature of 2-4 K for wafer-level characterization and integrate innovative electronics and machine-learning algorithms developed in this project with a 20 mK setup and use it for in-depth testing of selected devices from the other test setups. This will accelerate the design and selection of high-performing devices for quantum computing.

The ARCTIC partners will develop a novel, ultralow-noise and ultralow-drift DC-biasing and measurement system. This will include a high-channel-density Source Measure Unit (SMU) module that will showcase high characterization speed for cryogenic measurements, low noise, as well as economical per-channel cost. It will be possible to add many of these SMU modules to a dedicated host rack to reach the lowest noise level possible. Additionally, we will augment dedicated sequence processors to enable full spin-qubit control, support for LNA benchmarking and to accelerate high-throughput characterization at cryogenic temperatures.

Optimized metrology circuits and structures:

Testing of devices that operate at cryogenic temperature is a key step to assess the device quality, the device-to-device variability and to improve the manufacturing processes. Testing through the extraction of key parameters both at room temperature and at cryogenic temperature is therefore essential to ensure the assessment of the fabrication processes and to select the best-performing devices for time consuming mK measurements. State of the art testing of silicon quantum dots is nowadays limited to the study of a few key parameters and no clear link between low-temperature and high-temperature figures of merit has been established so far.

Partners will measure both traditional metrology structures, used as a reference for our measurements, and silicon quantum dots. We intend to establish which key parameters can effectively indicate the device quality and identify functional quantum devices for mK measurements. We will study the correlation between various metrics measured at room and at low temperature, to assess which parameters can be used for an effective pre-screening of silicon quantum dots above ultra-low temperature.